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ltc 2328-16 1 232816fa for more information www.linear.com/ltc2328-16 typical application features description 16-bit, 1msps, 10.24v true bipolar, pseudo-differential input adc with 93.5db snr the lt c ? 2328-16 is a low noise, high speed 16- bit suc- cessive approximation register ( sar) adc with pseudo- differential inputs. operating from a single 5 v supply, the ltc2328-16 has a 10.24 v true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. the ltc2328-16 achieves 1.5 lsb inl maximum, no missing codes at 16 bits with 93.5 db snr. the ltc2328-16 has an onboard single-shot capable reference buffer and low drift (20 ppm/c max ) 2.048 v temperature compensated reference. the ltc2328-16 also has a high speed spi-compatible serial interface that supports 1.8 v , 2.5 v , 3.3 v and 5 v logic while also featur - ing a daisy-chain mode. the fast 1 msps throughput with no cycle latency makes the ltc2328-16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considerations. the ltc2328-16 dissipates only 50 mw and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. a sleep mode is also provided to reduce the power consumption of the ltc2328-16 to 300 w for further power savings during inactive periods. l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765, 7961132. applications n 1msps throughput rate n 1.5 lsb inl (max) n guaranteed 16-bit no missing codes n pseudo-differential inputs n true bipolar input ranges 6.25 v , 10.24 v , 12.5 v n 93.5 db snr ( typ ) at f in = 2khz n ?111 db thd ( typ ) at f in = 2khz n guaranteed operation to 125c n single 5v supply n low drift (20ppm/c max) 2.048v internal reference n onboard single-shot capable reference buffer n no pipeline delay, no cycle latency n 1.8 v to 5v i/o voltages n spi-compatible serial i/o with daisy-chain mode n internal conversion clock n power dissipation 50mw ( typ ) n 16- lead msop package n programmable logic controllers n industrial process control n high speed data acquisition n portable or compact instrumentation n ate 32k point fft f s = 1msps, f in = 2khz frequency (khz) C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 232816 ta01b snr = 93.5dbthd = C111db sinad = 93.4db sfdr = C115db 0 100 200 300 500 400 +10.24vC10.24v C + sample clock 232816 ta01a 10f 0.1f 5v ref 1.8v to 5v 47f refbuf gnd chain rdl/sdi sdo sck busy cnv ltc2328-16 lt ? 1468 v dd 2.2f 100nf refin v ddlbyp ov dd in + in C downloaded from: http:///
ltc 2328-16 2 232816fa for more information www.linear.com/ltc2328-16 pin configuration absolute maximum ratings supply voltage (v dd ) .................................................. 6v supply voltage ( ov dd ) ................................................ 6v supply bypass voltage (v ddlbyp ) ........................... 3.2 v analog input voltage in + , in C .............................................. C16.5 v to 16.5 v refbuf ................................................................... 6v refin .................................................................. 2.8 v digital input voltage ( note 3) ........................... ( gnd C0.3 v) to ( ov dd + 0.3 v) digital output voltage ( note 3) ........................... ( gnd C0.3 v) to ( ov dd + 0.3 v) power dissipation .............................................. 500 mw operating temperature range ltc 2328 c ................................................ 0 c to 70 c ltc 2328 i ............................................. C40 c to 85 c ltc 2328 h .......................................... C40 c to 125 c storage temperature range .................. C65 c to 150 c (notes 1, 2) 12 3 4 5 6 7 8 v ddlbyp v dd gnd in + in C gnd refbuf refin 1615 14 13 12 11 10 9 gndov dd sdosck rdl/sdi busy chain cnv top view ms package 16-lead plastic msop t jmax = 150c, ja = 110c/w order information lead free finish tape and reel part marking* package description temperature range ltc2328cms-16#pbf ltc2328cms-16#trpbf 232816 16-lead plastic msop 0c to 70c ltc2328ims-16#pbf ltc2328ims-16#trpbf 232816 16-lead plastic msop C40c to 85c ltc2328hms-16#pbf ltc2328hms-16#trpbf 232816 16-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc 2328-16 3 232816fa for more information www.linear.com/ltc2328-16 electrical characteristics converter characteristics dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = ?1dbfs. (notes 4, 8) symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C2.5 ? v refbuf C 0.5 2.5 ? v refbuf + 0.5 v v in C absolute input range (in C ) (note 5) l C0.5 0.5 v v in + C v in C input differential voltage range v in = v in + C v in C l C2.5 ? v refbuf 2.5 ? v refbuf v i in analog input current l C7.8 4.8 ma c in analog input capacitance 5 pf r in analog input resistance 2.083 k cmrr input common mode rejection ratio f in = 500khz 66 db symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise 0.5 lsb rms inl integral linearity error (note 6) l C1.5 0.25 1.5 lsb dnl differential linearity error l C1 0.1 1 lsb bze bipolar zero-scale error (note 7) l C10 0 10 lsb bipolar zero-scale error drift 0.01 lsb/c fse bipolar full-scale error v refbuf = 4.096v (refbuf overdriven) (notes 7, 9) l C35 C35 lsb refin = 2.048v (note 7) l C45 45 lsb bipolar full-scale error drift 0.5 ppm/c symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio 6.25v range, f in = 2khz, refin = 1.25v l 87.1 90.4 db 10.24v range, f in = 2khz, refin = 2.048v l 90.2 93.4 db 12.5v range, f in = 2khz, refbuf = 5v l 90.5 94.2 db snr signal-to-noise ratio 6.25v range, f in = 2khz, refin = 1.25v l 87.5 90.5 db 10.24v range, f in = 2khz, refin = 2.048v l 91 93.5 db 12.5v range, f in = 2khz, refbuf = 5v l 92 94.5 db thd total harmonic distortion 6.25v range, f in = 2khz, refin = 1.25v l C108 C98 db 10.24v range, f in = 2khz, refin = 2.048v l C111 C98 db 12.5v range, f in = 2khz, refbuf = 5v l C106 C96 db sfdr spurious free dynamic range 6.25v range, f in = 2khz, refin = 1.25v l 98 110 db 10.24v range, f in = 2khz, refin = 2.048v l 98 113 db 12.5v range, f in = 2khz, refbuf = 5v l 96 108 db C3db input linear bandwidth 7 mhz aperture delay 500 ps aperture jitter 4 ps rms transient response full-scale step 0.5 s downloaded from: http:///
ltc 2328-16 4 232816fa for more information www.linear.com/ltc2328-16 internal reference characteristics reference buffer characteristics digital inputs and digital outputs power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v refin internal reference output voltage 2.043 2.048 2.053 v v refin temperature coefficient (note 14) l 2 20 ppm/c refin output impedance 15 k v refin line regulation v dd = 4.75v to 5.25v 0.08 mv/v refin input voltage range (refin overdriven) (note 5) 1.25 2.4 v symbol parameter conditions min typ max units v refbuf reference buffer output voltage v refin = 2.048v l 4.091 4.096 4.101 v refbuf input voltage range (refbuf overdriven) (notes 5, 9) l 2.5 5 v refbuf output impedance v refin = 0v 13 k i refbuf refbuf load current v refbuf = 5v (refbuf overdriven) (notes 9, 10) v refbuf = 5v, nap mode (refbuf overdriven) (note 9) l 0.89 0.39 1.2 ma ma symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma symbol parameter conditions min typ max units v dd supply voltage l 4.75 5 5.25 v ov dd supply voltage l 1.71 5.25 v i vdd i ovdd i nap i sleep supply current supply current nap mode current sleep mode current 1msps sample rate (in + = C10.24v, in C = 0v) 1msps sample rate (in + = in C = 0v) 1msps sample rate (c l = 20pf) conversion done (i vdd + i ovdd , in + = C10.24v, in C = 0v) sleep mode (i vdd + i ovdd ) l l l 14.5 10 0.4 8.4 60 16 10 225 ma ma ma ma a p d power dissipation nap mode sleep mode 1msps sample rate (in + = C10.24v, in C = 0v) 1msps sample rate (in + = in C = 0v) conversion done (i vdd + i ovdd , in + = C10.24v, in C = 0v) sleep mode (i vdd + i ovdd ) l l l 72.5 50 42 0.3 80 50 1.1 mw mw mw mw downloaded from: http:///
ltc 2328-16 5 232816fa for more information www.linear.com/ltc2328-16 adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above v dd or ov dd without latch-up.note 4: v dd = 5v, ov dd = 2.5v, 10.24v range, refin = 2.048v, f smpl = 1mhz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 10.24v input with refin = 2.048v.note 9: when refbuf is overdriven, the internal reference buffer must be turned off by setting refin = 0v.note 10: f smpl = 1mhz, i refbuf varies proportionally with sample rate. note 11: guaranteed by design, not subject to test. note 12: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 13: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising edge capture.note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. symbol parameter conditions min typ max units f smpl maximum sampling frequency l 1 msps t conv conversion time l 460 527 ns t acq acquisition time t acq = t cyc C t conv C t busylh (note 11) l 460 ns t cyc time between conversions l 1 s t cnvh cnv high time l 20 ns t busylh cnv to busy delay c l = 20pf l 13 ns t cnvl minimum low time for cnv (note 12) l 20 ns t quiet sck quiet time from cnv (note 11) l 20 ns t sck sck period (notes 12, 13) l 10 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 12) l 4 ns t hsdisck sdi hold time from sck (note 12) l 1 ns t sckch sck period in chain mode t sckch = t ssdisck + t dsdo (note 12) l 13.5 ns t dsdo sdo data valid delay from sck c l = 20pf, ov dd = 5.25v c l = 20pf, ov dd = 2.5v c l = 20pf, ov dd = 1.71v l l l 7.5 8 9.5 ns ns ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 11) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 11) l 5 ns t en bus enable time after rdl (note 12) l 16 ns t dis bus relinquish time after rdl (note 12) l 13 ns t wake refbuf wake-up time c refbuf = 47f, c refin = 100nf 200 ms figure 1. voltage levels for timing specifications 0.8 ? ov dd 0.2 ? ov dd 50% 50% 232816 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay downloaded from: http:///
ltc 2328-16 6 232816fa for more information www.linear.com/ltc2328-16 typical performance characteristics 32k point fft f s = 1msps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs temperature, f in = 2khz thd, harmonics vs temperature, f in = 2khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, f smpl = 1msps, unless otherwise noted. output code C1.0 inl error (lsb) 0.80.6 0.4 0 C0.8 C0.6 C0.4 C0.2 0.2 1.0 232816 g01 0 16384 32768 49152 65536 output code C0.5 dnl error (lsb) 0.40.3 0.2 0.1 0 C0.4 C0.3 C0.2 C0.1 0.5 232616 g02 0 16384 32768 49152 65536 code 32767 32768 32769 32770 0 counts 70003000 4000 50002000 1000 90008000 6000 232816 g03 = 0.5 frequency (khz) 0 60 snr, sinad (dbfs) 70 80 90 100 25 50 75 100 232816 g05 125 150 175 200 sinad snr frequency (khz) thd, harmonics (dbfs) C70C80 232816 g06 C150 C120C140 C130 C110 C100 C90 0 25 50 100 75 150 125 175 200 3rd 2nd thd input level (db) C40 92 magnitude (dbfs) 9493 95 96 C30 C20 232816 g07 C10 snr sinad 0 frequency (khz) C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 232816 g04 snr = 93.5dbthd = C111db sinad = 93.4db sfdr = C115db 0 100 200 300 500 400 temperature (c) C40 90 snr, sinad (dbfs) 91 93 94 95 C10 20 50 35 125 232816 g08 92 C25 5 65 80 95 110 96 sinad snr temperature (c) thd, harmonics (dbfs) C105C110 232816 g09 C125 C120 C115 3rd 2nd thd C40 C10 20 50 35 125 C25 5 65 80 95 110 downloaded from: http:///
ltc 2328-16 7 232816fa for more information www.linear.com/ltc2328-16 typical performance characteristics supply current vs temperature sleep current vs temperature internal reference output vs temperature internal reference output temperature coefficient distribution cmrr vs input frequency supply current vs sampling rate inl/dnl vs temperature full-scale error vs temperature offset error vs temperature t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, f smpl = 1msps, unless otherwise noted. drift (ppm/c) C10 0 number of parts 5 15 20 25 35 C8 0 4 232816 g16 10 30 C2 8 10 C6 C4 2 6 frequency (khz) 0 50 cmrr (db) 55 60 65 70 75 80 100 200 300 400 232816 g17 500 sampling frequency (khz) 0 supply current (ma) 8 10 12 900 800 232816 g18 6 4 0 200 400 600 100 1000 300 500 700 2 16 14 v dd (in + = C10.24v) v dd (in + = 10.24v) v dd (in + = 0v) ov dd temperature (c) inl, dnl error (lsb) 1.00.8 0.6 0.4 232816 g10 C1.0 C0.8 C0.6 C0.4 0 0.2 C0.2 max inl max dnl min inl min dnl C40 C10 20 50 35 125 C25 5 65 80 95 110 232816 g11 temperature (c) full-scale error (lsb) 2015 10 5 C20 C15 C10 C5 0 C40 C10 20 50 35 125 C25 5 65 80 95 110 232816 g12 temperature (c) offset error (lsb) 54 3 2 1 C5 C4 C3 C2 C1 0 C40 C10 20 50 35 125 C25 5 65 80 95 110 temperature (c) current (ma) 12 232816 g13 0 2 4 6 8 10 v dd (in + = in C = 0v) ov dd C40 C10 20 50 35 125 C25 5 65 80 95 110 temperature (c) current (a) 120 232816 g14 0 20 40 60 80 100 C40 C10 20 50 35 125 C25 5 65 80 95 110 232816 g15 temperature (c) C40 C25 C10 5 20 35 50 65 80 95 110 125 internal reference output (v) 2.04842.0483 2.0482 2.0481 2.0476 2.0477 2.0478 2.0479 2.0480 downloaded from: http:///
ltc 2328-16 8 232816fa for more information www.linear.com/ltc2328-16 pin functions v ddlbyp ( pin 1): 2.5 v supply bypass pin. the voltage on this pin is generated via an onboard regulator off of v dd . this pin must be bypassed with a 2.2 f ceramic capacitor to gnd.v dd ( pin 2): 5 v power supply. the range of v dd is 4.75 v to 5.25v. bypass v dd to gnd with a 10 f ceramic capacitor. gnd (pins 3, 6 and 16): ground. in + ( pin 4): analog input. in + operates differential with respect to in C with an in + -in C range of C2.5 ? v refbuf to 2.5 ? v refbuf . in ? ( pin 5): analog ground sense. in C has an input range of 500 mv with respect to gnd and must be tied to the ground plane or a remote sense.refbuf ( pin 7): reference buffer output. an onboard buffer nominally outputs 4.096 v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 47 f ceramic capacitor. the internal buffer driving this pin may be disabled by grounding its input at refin. once the buffer is disabled, an external refer - ence may overdrive this pin in the range of 2.5 v to 5 v. a resistive load greater than 500 k can be placed on the reference buffer output. refin ( pin 8): reference output/reference buffer input. an onboard bandgap reference nominally outputs 2.048 v at this pin. bypass this pin with a 100 nf ceramic capacitor to gnd to limit the reference output noise. if more accu - racy is desired, this pin may be overdriven by an external reference in the range of 1.25v to 2.4v.cnv ( pin 9): convert input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by ov dd . chain ( pin 10): chain mode selector pin. when low, the ltc2328-16 operates in normal mode and the rdl/sdi input pin functions to enable or disable sdo. when high, the ltc2328-16 operates in chain mode and the rdl/sdi pin functions as sdi, the daisy-chain serial data input. logic levels are determined by ov dd . busy ( pin 11): busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by ov dd . rdl/sdi ( pin 12): when chain is low, the part is in nor- mal mode and the pin is treated as a bus enabling input. when chain is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another adc in the daisy chain is input. logic levels are determined by ov dd . sck ( pin 13): serial data clock input. when sdo is enabled , the conversion result or daisy-chain data from another adc is shifted out on the rising edges of this clock msb first. logic levels are determined by ov dd . sdo ( pin 14): serial data output. the conversion result or daisy-chain data is output on this pin on each rising edge of sck msb first. the output data is in 2 s complement format. logic levels are determined by ov dd . ov dd ( pin 15): i/o interface digital power. the range of ov dd is 1.71 v to 5.25 v. this supply is nominally set to the same supply as the host interface (1.8 v , 2.5 v , 3.3 v, or 5v). bypass ov dd to gnd with a 0.1f capacitor. downloaded from: http:///
ltc 2328-16 9 232816fa for more information www.linear.com/ltc2328-16 functional block diagram timing diagram conversion timing using the serial interface refbuf = 2.5v to 5v refin = 1.25v to 2.4v in + v dd = 5v ov dd = 1.8v to 5v in C v ddlbyp = 2.5v chain 0.63 buffer 2 reference buffer r 4r cnv gnd busy sdosck rdl/sdi control logic ldo 2.048v reference 16-bit sampling adc spi port +C 232816 bd01 15k 4r r nap and acquire convert d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo sck cnv chain, rdl/sdi = 0busy 232816 td01 downloaded from: http:///
ltc 2328-16 10 232816fa for more information www.linear.com/ltc2328-16 applications information overview the ltc2328-16 is a low noise, high speed 16- bit suc- cessive approximation register ( sar) adc with pseudo- differential inputs. operating from a single 5 v supply, the ltc2328-16 has a 10.24 v true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. the ltc2328-16 achieves 1.5 lsb inl maximum, no missing codes at 16- bits and 93.5 db snr. the ltc2328-16 has an onboard single-shot capable reference buffer and low drift (20 ppm/c max ) 2.048 v temperature-compensated reference. the ltc2328-16 also has a high speed spi-compatible serial interface that supports 1.8 v , 2.5 v , 3.3 v and 5 v logic while also featur- ing a daisy-chain mode. the fast 1 msps throughput with no cycle latency makes the ltc2328-16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considerations. the ltc2328-16 dissipates only 50 mw and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. a sleep mode is also provided to reduce the power consumption of the ltc2328-16 to 300 w for further power savings during inactive periods. converter operation the ltc2328-16 operates in two phases. during the acquisition phase, the charge redistribution capacitor d/a converter ( cdac) is connected to the outputs of the resistor divider networks that pins in + and in C drive to sample an attenuated and level-shifted version of the pseudo-differential analog input voltage as shown in fig- ure?3. a rising edge on the cnv pin initiates a conversion. during the conversion phase, the 16- bit cdac is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted frac- tions of the reference voltage ( e.g. v refbuf /2, v refbuf /4 v refbuf /65536) using the differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 16-bit digital output code for serial transfer. figure 2. ltc2328-16 transfer function transfer function the ltc2328-16 digitizes the full-scale voltage of 2.5 ? refbuf into 2 16 levels, resulting in an lsb size of 312.5 v with refbuf = 4.096 v . the ideal transfer function is shown in figure 2. the output data is in 2 s complement format. analog input the analog inputs of the ltc2328-16 are pseudo-differen- tial in order to reduce any unwanted signal that is common to both inputs. the analog inputs can be modeled by the equivalent circuit shown in figure 3. the back-to-back diodes at the inputs form clamps that provide esd protec- tion. each input drives a resistor divider network that has figure 3. the equivalent circuit for the differential analog input of the ltc2328-16 r on 50 400 c in 45pf r on 50 0.63 ? v refbuf c in 45pf in + in C bias voltage 1.6k1.6k 400 0.63 ? v refbuf 232816 f03 input voltage (v) 0v output code (twos complement) C1 lsb 232816 f02 011...111 011...110000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 C 1lsb Cfsr/2 fsr = +fs C Cfs1lsb = fsr/65536 downloaded from: http:///
ltc 2328-16 11 232816fa for more information www.linear.com/ltc2328-16 applications information figure 4. input signal chain a total impedance of 2 k. the resistor divider network attenuates and level shifts the 2.5 ? refbuf true bipolar signal swing of each input to the 0- refbuf input signal swing of the adc core. in the acquisition phase , 45 pf ( c in ) from the sampling cdac in series with approximately 50 (r on ) from the on-resistance of the sampling switch is connected to the output of the resistor divider network. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the adc core and resistor divider network. the in + input of the adc core draws a current spike while charging the c in capacitor during acquisition.input drive circuits a low impedance source can directly drive the high im- pedance input of the ltc2328-16 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis- tortion performance of the adc. minimizing settling time is important even for dc inputs, because the adc input draws a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog input of the ltc2328-16. the amplifier provides low output impedance to minimize gain error and allows for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc input which draws a small current spike during acquisition.input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. the simple 1- pole rc lowpass filter shown in figure 4 is sufficient for many applications. the input resistor divider network, sampling switch on- resistance ( r on ) and the sample capacitor ( c in ) form a second lowpass filter that limits the input bandwidth to the adc core to 7 mhz. a buffer amplifier with a low noise density must be selected to minimize the degradation of the snr over this bandwidth. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems.pseudo-differential bipolar inputs for most applications, we recommend the low power lt1468 adc driver to drive the ltc2328-16. with a low noise density of 5 nv/ hz and a low supply current of 3 ma, the lt1468 is flexible and may be configured to convert signals of various amplitudes to the 10.24 v input range of the ltc2328-16.to achieve the full distortion performance of the ltc2328-16, a low distortion single-ended signal source driven through the lt1468 configured as a unity-gain buffer as shown in figure 4 can be used to get the full data sheet thd specification of C111db. adc reference there are three ways of providing the adc reference. the first is to use both the internal reference and reference buffer. the second is to externally overdrive the internal reference and use the internal reference buffer. the third is to disable the internal reference buffer and overdrive the refbuf pin from an external source. the following tables give examples of these cases and the resulting bipolar input ranges. 66nf 50 bw = 48khz 10.24v C + lt1468 ltc2328-16 in + in C 232816 f04 downloaded from: http:///
ltc 2328-16 12 232816fa for more information www.linear.com/ltc2328-16 applications information figure 5a. ltc2328-16 internal reference circuit table 1. internal reference with internal buffer refin refbuf bipolar input range 2.048v 4.096v 10.24v table 2. external reference with internal buffer refin (overdrive) refbuf bipolar input range 1.25v (min) 2.5v 6.25v 2.048v 4.096v 10.24v 2.4v (max) 4.8v 12v table 3. external reference unbuffered refin refbuf (overdrive) bipolar input range 0v 2.5v (min) 6.25v 0v 5v (max) 12.5v internal reference with internal buffer the ltc2328-16 has an on-chip, low noise, low drift (20ppm/ c max), temperature compensated bandgap reference that is factory trimmed to 2.048 v. it is internally connected to a reference buffer as shown in figure 5 a and is available at refin ( pin 8). refin should be bypassed to gnd with a 100 nf ceramic capacitor to minimize noise. the reference buffer gains the refin voltage by 2 to 4.096 v at refbuf ( pin 7). so the input range is 10.24 v, as shown in table 1. bypass refbuf to gnd with at least a 47 f ceramic capacitor ( x7r , 10 v , 1210 size) to compensate the reference buffer and minimize noise. external reference with internal buffer if more accuracy and/or lower drift is desired, refin can be easily overdriven by an external reference since a 15 k resistor is in series with the reference as shown in figure ?5 b. refin can be overdriven in the range from 1.25v to 2.4 v. the resulting voltage at refbuf will be 2???refin. so the input range is 5 ? refin, as shown in table 2. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power, and high accuracy, the ltc6655-2.048 is well suited for use with the ltc2328-16 when overdriving the internal reference. the ltc6655-2.048 offers 0.025% ( max) initial accuracy and 2 ppm/c ( max) temperature coefficient for high pre - cision applications. the ltc6655-2.048 is fully specified over the h-grade temperature range and complements the extended temperature range of the ltc2328-16 up to 125 c . bypassing the ltc6655-2.048 with a 2.7 f to 100 f ceramic capacitor close to the refin pin is recommended. external reference unbuffered the internal reference buffer can also be overdriven from 2.5v to 5 v with an external reference at refbuf as shown in figure 5 c. so the input ranges are 6.25 v to 12.5 v, respectively, as shown in table 3. to do so, refin must be grounded to disable the reference buffer. a 13 k resistor loads the refbuf pin when the reference buffer is disabled . to maximize the input signal swing and corresponding snr, the ltc6655-5 is recommended when overdriv - ing refbuf . the ltc6655-5 offers the same small size, accuracy, drift and extended temperature range as the ltc6655-2.048. by using this 5 v reference, an snr of 94.5db can be achieved. bypassing the ltc6655-5 with a 47 f ceramic capacitor ( x5r , 0805 size) close to the refbuf pin is recommended.the refbuf pin of the ltc2328-16 draws a charge ( q conv ) from the external bypass capacitor during each conversion cycle. if the internal reference buffer is overdriven, the external reference must provide all of this charge with a dc current equivalent to i refbuf = q conv /t cyc . thus, the dc current draw of refbuf depends on the sampling ltc2328-16 bandgap reference 232816 f05a 47f 100nf 6.5k refbuf refin 15k 6.5k reference buffer gnd ? + downloaded from: http:///
ltc 2328-16 13 232816fa for more information www.linear.com/ltc2328-16 applications information figure 5b. using the ltc6655-2.048 as an external reference figure 5c. overdriving refbuf using the ltc6655-5 figure 6. cnv waveform showing burst sampling of the output code. if an external reference is used to overdrive refbuf, the fast settling ltc6655-5 reference is recommended. internal reference buffer transient response for optimum transient performance, the internal reference buffer should be used. the internal reference buffer uses a proprietary design that results in an output voltage change at refbuf of less than 0.25 lsb when responding to a sud - den burst of conversions. this makes the internal reference buffer of the ltc2328-16 truly single - shot capable since the first sample taken after idling will yield the same result as a sample taken after the transient response of the internal reference buffer has settled. figure 7 shows the transient responses of the ltc2328-16 with the internal reference buffer and with the internal reference buffer overdriven by the ltc6655-5, both with a bypass capacitance of 47 f. rate and output code. in applications where a burst of samples is taken after idling for long periods, as shown in figure?6, i refbuf quickly goes from approximately 390 a to a maximum of 1.2 ma for refbuf = 5 v at 1 msps. this step in dc current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at refbuf will affect the accuracy figure 7. transient response of the ltc2328-16 time (s) deviation from final value (lsb) 0.5 0 C0.5C1.0 232816 f07 C2.0 C1.5 0 900 800 700 600 500 400 300 200 100 1000 internal reference buffer external source on refbuf cnv idle period idle period 232816 f06 ltc2328-16 bandgap reference ltc6655-2.048 232816 f05b 47f 2.7f 6.5k refbuf refin 15k 6.5k reference buffer gnd ? + ltc2328-16 gnd bandgap reference ltc6655-5 232816 f05c 47f 6.5k refbuf refin 15k 6.5k reference buffer ? + downloaded from: http:///
ltc 2328-16 14 232816fa for more information www.linear.com/ltc2328-16 applications information dynamic performance fast fourier transform ( fft ) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the ltc2328-16 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio ( sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 8 shows that the ltc2328-16 achieves a typical sinad of 93.4 db at a 1 mhz sampling rate with a 2khz input.signal-to-noise ratio (snr) the signal-to-noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 8 shows that the ltc2328-16 achieves a typical snr of 93.5 db at a 1mhz sampling rate with a 2khz input. total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself . the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency ( f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v 1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics. power considerations the ltc2328-16 provides two power supply pins: the 5 v power supply ( v dd ), and the digital input/output interface power supply ( ov dd ). the flexible ov dd supply allows the ltc2328-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5 v and 3.3 v systems.power supply sequencing the ltc2328-16 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2328-16 has a power-on reset ( por) circuit that will reset the ltc2328-16 at initial power-up or whenever the power supply voltage drops below 2 v. once the supply voltage reenters the nominal supply voltage range, the por will re-initialize the adc. no conversions should be initiated until 200 s after a por event to ensure the re-initialization period has ended. any conversions initiated before this time will produce invalid results.timing and control cnv timing the ltc2328-16 conversion is controlled by cnv. a ris - ing edge on cnv will start a conversion and power up the ltc2328-16. once a conversion has been initiated, it cannot be restarted until the conversion is complete. figure 8. 32k point fft of the ltc2328-16 frequency (khz) C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 232816 f08 snr = 93.5dbthd = C111db sinad = 93.4db sfdr = C115db 0 100 200 300 500 400 downloaded from: http:///
ltc 2328-16 15 232816fa for more information www.linear.com/ltc2328-16 applications information figure 9. power supply current of the ltc2328-16 versus sampling rate for optimum performance, cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40 ns from the start of the conversion or after the conversion has been completed. once the conversion has completed, the ltc2328-16 powers down and begins acquiring the input signal.internal conversion clock the ltc2328-16 has an internal clock that is trimmed to achieve a maximum conversion time of 527 ns. with a mini - mum acquisition time of 460 ns, throughput performance of 1 msps is guaranteed without any external adjustments. auto nap mode the ltc2328-16 automatically enters nap mode after a conversion has been completed and completely powers up once a new conversion is initiated on the rising edge of cnv. during nap mode, only the adc core powers down and all other circuits remain active. during nap, data from the last conversion can be clocked out. the auto nap mode feature will reduce the power dissipation of the ltc2328-16 as the sampling frequency is reduced. since full power is consumed only during a conversion, the adc core of the ltc2328-16 remains powered down for a larger fraction of the conversion cycle ( t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 9. sleep mode the auto nap mode feature provides limited power savings since only the adc core powers down. to obtain greater power savings, the ltc2328-16 provides a sleep mode. during sleep mode, the entire part is powered down except for a small standby current resulting in a power dissipation of 300 w. to enter sleep mode, toggle cnv twice with no intervening rising edge on sck. the part will enter sleep mode on the falling edge of busy from the last conversion initiated. once in sleep mode, a rising edge on sck will wake the part up. upon emerging from sleep mode, wait t wake ms before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at refin and refbuf. (refer to the timing diagrams section for more detailed timing information about sleep mode.) digital interface the ltc2328-16 has a serial digital interface. the flexible ov dd supply allows the ltc2328-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5v and 3.3v systems. the serial output data is clocked out on the sdo pin when an external clock is applied to the sck pin if sdo is enabled . clocking out the data after the conversion will yield the best performance. with a shift clock frequency of at least 40mhz, a 1 msps throughput is still achieved. the serial output data changes state on the rising edge of sck and can be captured on the falling edge or next rising edge of sck. d15 remains valid till the first rising edge of sck. the serial interface on the ltc2328-16 is simple and straightforward to use. the following sections describe the operation of the ltc2328-16. several modes are provided depending on whether a single or multiple adcs share the spi bus or are daisy-chained. sampling frequency (khz) 1 supply current (ma) 8 10 12 900 800 232816 f09 6 4 0 200 400 600 100 1000 300 500 700 2 16 14 v dd (in + = C10.24v) v dd (in + = 10.24v) v dd (in + = 0v) ov dd downloaded from: http:///
ltc 2328-16 16 232816fa for more information www.linear.com/ltc2328-16 timing diagrams normal mode, single device when chain = 0, the ltc2328-16 operates in normal mode. in normal mode, rdl/sdi enables or disables the serial data output pin sdo. if rdl/sdi is high, sdo is in high impedance. if rdl / sdi is low, sdo is driven. figure ?1 0 shows a single ltc2328-16 operated in normal mode with chain and rdl/sdi tied to ground. with rdl/sdi grounded, sdo is enabled and the msb(d15) of the new conversion data is available at the falling edge of busy. this is the simplest way to operate the ltc2328-16. figure 10. using a single ltc2328-16 in normal mode cnv ltc2328-16 busy convert irq data in digital host clk sdo sck rdl/sdi chain 232816 f10 convert convert t acq t acq = t cyc C t conv C t busylh nap and acquire nap and acquire cnv chain = 0 busy sck sdo rdl/sdi = 0 t busylh t dsdobusyl t sck t hsdo t sckh t quiet t sckl t dsdo t conv t cnvh t cyc t cnvl d15 d14 d13 d1 d0 1 2 3 14 15 16 downloaded from: http:///
ltc 2328-16 17 232816fa for more information www.linear.com/ltc2328-16 timing diagrams normal mode, multiple devicesfigure 11 shows multiple ltc2328-16 devices operating in normal mode ( chain = 0) sharing cnv, sck and sdo. by sharing cnv, sck and sdo, the number of required signals to operate multiple adcs in parallel is reduced. since sdo is shared, the rdl/sdi input of each adc must be used to allow only one ltc2328-16 to drive sdo at a time in order to avoid bus conflicts. as shown in figure 11, the rdl/sdi inputs idle high and are individually brought low to read data out of each device between conversions. when rdl/sdi is brought low, the msb of the selected device is output onto sdo. figure 11. normal mode with multiple devices sharing cnv, sck, and sdo rdl b rdl a convert irq data in digital host clk cnv ltc2328-16 sdo a sck rdl/sdi cnv ltc2328-16 sdo b sck rdl/sdi chain busy chain 232818 f11 d15 a sdo sck cnv busy chain = 0 rdl/sdi b rdl/sdi a d15 b d14 b d1 b d0 b d13 b d14 a d13 a d1 a d0 a hi-z hi-z hi-z t en t hsdo t dsdo t dis t sckl t sckh t cnvl 1 2 3 14 15 16 17 18 19 30 31 32 t sck convert convert t quiet t conv t busylh nap and acquire nap and acquire downloaded from: http:///
ltc 2328-16 18 232816fa for more information www.linear.com/ltc2328-16 timing diagrams chain mode, multiple deviceswhen chain = ov dd , the ltc2328-16 operates in chain mode. in chain mode, sdo is always enabled and rdl/sdi ser ves as the serial data input pin ( sdi) where daisy-chain data output from another adc can be input. this is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. figure 12 shows an example with two daisy-chained devices. the msb of converter a will appear at sdo of converter b after 16 sck cycles. the msb of converter a is clocked in at the sdi/rdl pin of converter b on the rising edge of the first sck. figure 12. chain mode timing diagram ov dd convert irq data in digital host clk cnv ltc2328-16 busy sdo b sck rdl/sdi cnv ltc2328-16 sdo a sck rdl/sdi chain ov dd chain 232816 f12 d0 a d1 a d14 a d15 a d13 b d14 b d15 b sdo b sdo a = rdl/sdi b rdl/sdi a = 0 d0 b d1 b d13 a d14 a d15 a d0 a d1 a 1 2 3 14 15 16 17 18 30 31 32 t dsdobusyl t ssdisck t hsdisck t busylh t conv t hsdo t dsdo t sckl t sckh t sckch t cnvl t cyc convert convert sck cnv busy chain = ov dd t quiet nap and acquire nap and acquire downloaded from: http:///
ltc 2328-16 19 232816fa for more information www.linear.com/ltc2328-16 timing diagrams sleep modeto enter sleep mode, toggle cnv twice with no interven- ing rising edge on sck as shown in figure 13. the part will enter sleep mode on the falling edge of busy from the last conversion initiated. once in sleep mode, a rising edge on sck will wake the part up. upon emerging from sleep mode, wait t wake ms before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at refin and refbuf. figure 13. sleep mode timing diagram 232816 f13 convert convert sleep nap and acquire cnv busy sck t busylh t wake t conv t cnvh convert convert sleep nap and acquire nap and acquire cnv busy sck t busylh t wake t conv convert t conv t cnvh chain = dont care rdl/sdi = dont care chain = dont care rdl/sdi = dont care downloaded from: http:///
ltc 2328-16 20 232816fa for more information www.linear.com/ltc2328-16 board layout to obtain the best performance from the ltc2328-16 a printed circuit board ( pcb) is recommended. layout for pcb should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layoutthe following is an example of a recommended pcb layout . a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1908, the evaluation kit for the ltc2328-16. partial top silkscreen downloaded from: http:///
ltc 2328-16 21 232816fa for more information www.linear.com/ltc2328-16 board layout partial layer 1 component side partial layer 2 ground plane downloaded from: http:///
ltc 2328-16 22 232816fa for more information www.linear.com/ltc2328-16 partial layer 3 power plane partial layer 4 bottom layer board layout downloaded from: http:///
ltc 2328-16 23 232816fa for more information www.linear.com/ltc2328-16 board layout partial schematic of demo board downloaded from: http:///
ltc 2328-16 24 232816fa for more information www.linear.com/ltc2328-16 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.10 (.201) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev a) downloaded from: http:///
ltc 2328-16 25 232816fa for more information www.linear.com/ltc2328-16 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 12/14 change t acq time units to ns 5 downloaded from: http:///
ltc 2328-16 26 232816fa for more information www.linear.com/ltc2328-16 ? linear technology corporation 2014 lt 1214 rev a ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2328-16 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 related parts typical application part number description comments adcs ltc2338-18/ltc2337-18/ltc2336-18 18-bit, 1msps/500ksps/250ksps serial, low power adc 5v supply, 10.24v t rue bipolar, differential input, 100db snr, pin-compatible family in msop-16 package ltc2328-18/ltc2327-18/ltc2326-18 18-bit, 1msps/500ksps/250ksps serial, low power adc 5v supply, 10.24v true bipolar, pseudo-differential input, 95db snr, pin-compatible family in msop-16 package ltc2378-20/ltc2377-20/ ltc2376-20 20-bit, 1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 0.5ppm inl, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2379-18/ltc2378-18/ ltc2377-18/ltc2376-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2369-18/ltc2368-18/ltc2367-18/ltc2364-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 96.5db snr, 0v to 5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2370-16/ltc2368-16/ltc2367-16/ltc2364-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 94db snr, 0v to 5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2389-18/ltc2389-16 18-bit/16-bit, 2.5msps parallel/serial adc 5v supply, pin-configurable input range, 99.8db/96db snr, parallel or serial i/o 7mm 7mm lqfp-48 and qfn-48 packages dacs ltc2756/ltc2757 18-bit, single serial/parallel i out softspan? dac 1lsb inl/dnl, software-selectable ranges, ssop-28/7mm 7mm lqfp-48 package ltc2641 16-bit/14-bit/12-bit single serial v out dac 1lsb inl /dnl, msop-8 package, 0v to 5v output ltc2630 12-bit/10-bit/8-bit single v out dacs 1lsb inl (12 bits), internal reference, sc70 6-pin package references ltc6655 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt1468/lt1469 single/dual 90mhz, 22v/s, 16-bit accurate op amp low input offset: 75v/125v lt1468 configured to buffer a 10.24v single-ended signal into the ltc2328-16 232816 ta02 ltc2328-16 in + v dd 5v in C C10.24v +10.24v 47f refbuf C15v 15v lt1468 100nf refin C + 2 6 7 4 3 downloaded from: http:///

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